1. Field of the Invention
The present invention relates to fabrication of integrated circuit devices and, more particularly, to a field effect transistor (FET) with an improved performance reliability regarding the injection of charge carriers into the gate insulation layer separating the gate electrode from the drain, source and channel regions of the transistor, and a method of fabricating the same.
2. Description of the Related Art
The process of manufacturing integrated circuits (IC) involves the fabrication of numerous insulated gate field effect transistors, such as metal oxide semiconductor (MOS) or metal insulation semiconductor (MIS) transistors. In order to be able to increase integration density and improve device performance, for instance, with respect to signal processing time and power consumption, feature sizes of the transistor structures are steadily decreasing. In particular, the reduced thickness of the insulation layer between the gate electrode and the channel region, as well as the reduced channel length, i.e., the lateral extension of the channel between the source and drain regions of the transistor, may cause undesirable effects in the performance of the device. These adverse effects become more important as the feature sizes of such devices continue to decrease.
One important issue in this respect is the so-called xe2x80x9chot carrier injectionxe2x80x9d effects that occur when device dimensions are reduced, but the supply voltage is maintained at a constant level, e.g., 5 volts. Due to the smaller device dimensions, the electric field between the source and drain regions of the transistor is enhanced compared to a device having a larger channel length when the same supply voltage is used. Additionally, this electric field is further enhanced by the electric fields of the dopant atoms in the drain and source regions and leads to an intensity peak of the superimposed field. In a MOS transistor, for example, the electrons in the channel may possibly gain sufficient energy to be injected into the gate insulation layer. This charge accumulation inside the gate insulation layer may cause longterm device degradation in that the threshold voltage of the device is raised and the transconductance is reduced. This effect predominantly occurs at the peripheral portions of the gate insulation layer, since the electric field created across the gate insulation layer is superimposed with the electric field created by the voltage across the drain and the source regions and the doped portions of these regions that extend beyond or underneath the gate insulation layer.
Although it is preferable to have a very thin gate insulation layer so as to effectively create the inversion layer in the channel region, the electric field created when a gate voltage is applied enhances the peak of the electric field near the peripheral portion of the gate insulation layer. This strongly contributes to the undesirable injection of electrons into this peripheral portion of the gate insulation layer. In order to reduce the peak of the electric field near the peripheral portions of the gate insulation layer, a lightly doped region extending beyond or underneath the peripheral portions of the gate insulation layer is formed. In highly sophisticated FET transistors, efforts are made to minimize the electrical resistance between the drain and source contacts. For example, this may involve reducing the channel length of the device and decreasing the gate insulation layer thickness to increase the electric field which affects the channel. The overall resistance of the device then strongly depends on the intrinsic resistance of the source region and, in particular, on the resistance of the drain, since the channel builds up starting from the source and becomes continually narrower as it approaches the lightly doped drain region.
With reference to FIGS. 1A-1C, an illustrative example of forming a MOS transistor according to a typical prior art process will be described. It is to be noted that FIGS. 1A-1C, as well as the following drawings of this application, are merely schematic depictions of the various stages in manufacturing the considered illustrative device. The person skilled in the relevant art will readily appreciate that the dimensions shown in the figures are not true to scale and that different portions or layers are not separated by sharp boundaries as reflected in the drawings but may instead comprise continuous transitions. Furthermore, various process steps as described below may be performed differently depending on particular design requirements. Moreover, in this description, only the relevant steps and portions of the device which are necessary for the understanding of the present invention are considered.
FIG. 1A depicts a schematic cross-section through a MOS semiconductor device at a specific stage of the manufacturing process. Within a silicon substrate 1, shallow trench isolations 2 comprised of an insulating material, e.g., silicon dioxide, are formed in the substrate 1. The trench isolations 2 define an active region 3 in which a channel, drain and source regions will be formed. Over the active region 3, a gate electrode 4 made of, for example, polycrystalline silicon, is formed. The gate electrode 4 is separated from the active region 3 by a thin gate insulation layer 5 comprised of, for example, silicon dioxide. The process steps involved in patterning the gate electrode 4 and the gate insulation layer 5 are of common knowledge to the skilled person and will herein not be described in detail.
FIG. 1B shows a schematic cross-section through the semiconductor device of FIG. 1A in an advanced fabrication stage. A thin screen oxide layer 6 is formed over the structure as shown in FIG. 1A. Screen oxide layer 6 may be deposited by chemical vapor deposition (CVD) or may be grown thermally by means of a furnace process. Lightly doped regions 7 are formed within the active region 3 extending from the shallow trench isolations 2 toward the gate electrode 4. The lightly doped regions 7 are produced by an ion implantation process with a small dose, wherein the direction of movement of the ions is substantially perpendicular to the surface of the substrate 1.
FIG. 1C shows a schematic depiction of the device in a further advanced fabrication stage. The screen oxide layer 6 has been removed and sidewall spacers 8 comprised of, for example, silicon dioxide, are formed on the sidewalls of the gate electrode 4. Subsequently, a further implantation step is performed to create a highly doped drain and source region 9, respectively. Then, the implanted regions 9 and 7 are activated by a rapid thermal anneal process that results in a lateral diffusion of the junctions between the doped drain and source regions and the inversely doped active region 3. Accordingly, the lightly doped regions 7 partially extend beyond or underneath the gate insulation layer 5. As previously discussed, such an arrangement may cause charge carriers to be injected into the gate insulation layer 5, thereby decreasing device reliability.
In view of the above-mentioned problems, a need exists for a transistor having an increased performance reliability and for a method of fabricating such a device. The present invention is directed to a method of making a semiconductor device that solves, or at least reduces, some or all of the aforementioned problems.
The present invention is directed to a transistor having a peripherally increased gate insulation thickness, and a method of making same. In one illustrative embodiment, the transistor is comprised of a substrate in which an active region is defined, a gate electrode formed above the active region, and a gate insulation layer positioned between the substrate and the gate electrode, wherein an edge region of the gate insulation layer is thicker than the middle region of the gate insulation layer.
In one illustrative embodiment, the method disclosed herein is comprised of providing a semiconductor substrate having an active region formed therein, forming a gate insulation layer above the active region, and forming a gate electrode material above the gate insulation layer. The method further comprises patterning the gate electrode material to define a gate electrode, and increasing a thickness of the gate insulation layer at an edge region thereof.